From 724cc66faa2ef6e23e0fd910d58683f7eee3953d Mon Sep 17 00:00:00 2001 From: raphy Date: Sun, 12 Nov 2023 07:00:44 +0100 Subject: [PATCH] fixed typos --- spec.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/spec.md b/spec.md index ff2931f..37d3c4b 100644 --- a/spec.md +++ b/spec.md @@ -10,7 +10,7 @@ Since I'm studying riscV, this will be a lot riscv inspired. The gravejit virtual machine sports 16 16-bit registers (plus the program counter!) and 16 operations. -Here is the list of registers togheter with memonics. +Here is the list of registers together with memonics. ``` 0 : zero // register 0 is always 0. 1 : ra // return address @@ -56,7 +56,7 @@ pc: program counter. ### Operation formats: -Each istruction is 16 bits long. +Each instruction is 16 bits long. The first 4 most-significant bits are the opcode. Constants (c in the above table) are always considered signed, and written in two's compliment. Sign extension also takes place whenever needed.